Technical Field
This disclosure relates to determining the power being used by digital circuits and to power management and other applications for this information.
Description of Related Art
--Introduction
Dynamic power management algorithms can improve the way computing systems utilize available power. Algorithms can rely on power measurements or estimates to make intelligent power management decisions. For emerging computer technologies, accuracy and resolution of power measurement may play a greater role in low power system designs and dynamic power management plans.
Power consumed by an electric circuit can be directly measured with current sense resistors, amplifiers, and analog-to-digital converters (ADCs). This may be the most intuitive way of measuring power accurately in digital circuits. However, it may introduce practical challenges for emerging platforms such as mobile phones and systems-on-chips (SOCs). These challenges may include scalability, instrumentation error, and ADC related resource overhead.
System developers have been interested in measuring power at a board level for low-power operation and at chip level to increase manufacturing yield. Broadly speaking, three techniques have been considered: (1) direct measurement with ADC; (2) power model based estimation; and (3) a hybrid method using sensors and power models.
--Dedicated Analog to Digital Converters
Recent works, like Low Power Energy Aware Processing (LEAP) platform and MIT's recent on-chip ADC based power minimization technique have been demonstrated to save up to 60% and 2× power in embedded systems, respectively. However, such techniques may suffer instrumentation errors, aging, scalability, and delays associated with ADCs. Also, as the intrinsic gain of transistors decreases with manufacturing technology scaling, it may become harder to implement such technologies using on-chip ADCs.
--Power Model Based Estimation
This type of power estimation may rely on an accurate, on-line extraction of a power model for each architecture component from workload information and external ADC based power measurement. This method may eliminate the need for ADCs on-chip. However, the system may rely on values from external ADCs over long windows of time to build workload specific power models. With significant differences found in resulting power models across different workloads, errors can be evident, even at low sampling rates and fewer channels, as shown below in Table 1.
--Estimation Using Built-In Event Counters
More recent on-chip power measurement techniques add another dimension to the model based technique by leveraging information collected by built-in event counters on processors. Using counter values, workloads, and ADC measurements, effective capacitances of various logic blocks can be more accurately modeled. Given a sufficient number of power models, counter values can be used to estimate the power dissipated by various components at a given time.
For ICs with built-in event counters—common in general purpose processors—the improvements in on-chip power estimation may come at a relatively low overhead, since there is no need to change existing hardware. However, this technique may suffer similar kinds of problems to those associated with inaccuracies in the power modeling technique described above, especially when presented with an increasing number of micro-architecture components. Furthermore, this technique may require highly complex algorithms to obtain power numbers. This may require longer times and greater computation resources to make intelligent power management decisions.
--Logical Partition Power Measurement
Another low power digital design has been parametric clustering of logic to optimize power. Power may be estimated through simulation to optimize logic clusters to achieve minimum power. Some efforts also measure the power of the logical partitions to evaluate the design for possible gains in power reduction through logic re-synthesis. To enable such a system to provide designers with practical feedback on their work, FPGA and ASIC manufacturers have provided an on-chip tool to measure power for a limited number of partitions which uses on-chip ADCs or design model simulation. However, these methods may have large errors due to routing patterns, ADC instrumentation, and/or model accuracy and limited channels that might mislead.